This page describes the instruction set for the TMS9900
Addressing Modes
The TMS9900 has 8 addressing modes which determine how operands are provided to the instruction.
Workspace Register Addressing
Operand is a specified workspace register.
Workspace register addressing is indicated by a decimal or hexadecimal number, the decimal register number can optionally be preceded by an R
Workspace Register Indirect Addressing
Operand is specified by the address contained in a workspace register
Indirect workspace register addressing is indicated by a workspace register reference preceded by an *
Symbolic Memory Addressing
Operand is specified by an immediate address
Symbolic Memory Addressing is indicated by a number or a label representing the address preceded by @
Indexed Memory Addressing
Operand is specified by an immediate address added to a workspace register. Workspace register 0 can't be used for indexing
Indexed Memory Addressing is indicated by an address preceded by @ and followed by a workspace register reference in parenthesis
Workspace Register Indirect autoincrement Addressing
Operand is specified by the address contained in a workspace register and incremented by the operand size afterwards
Workspace Register Indirect autoincrement addressing is indicated by a workspace register reference preceded by * and followed by +
Program Counter Relative Addressing
Operand is an offset that will get added to the program counter
Relative addressing is indicated by a label or an address, the assembler will calculate the offset
CRU Bit Addressing
Operand is an offset that gets applied to the CRU base register (R12)
CRU Bit addressing is indicated by a number or symbol
Immediate Addressing
Operand is a specified value
Instruction Formats
Fields
A subscript s indicates that the field is for the source operand and a subscript d indicates that the field is for the destination operand
Op Code
Value that defines the instruction
Byte indicator (B)
1 for byte instruction, 0 for word instruction
Addressing Mode (T)
Subscript identifies which operand the addressing mode field applies to
0 = Workspace Register
1 = Workspace Register Indirect
2 = Symbolic Memory/Indexed Memory
3 = Workspace Register Indirect Autoincrement
Destination (D)
The destination workspace register
Source (S)
The source workspace register
Displacement
Signed displacement value
Count (C)
Bit or shift count
Workspace Register (W)
The workspace register to be modified
Extended Operation (X)
The extended operation to be performed
Data
Represents an integer value used by the instruction
Formats
Source and Destination Addresses are only present if Symbolic Memory or Indexed Memory mode is used
Format I – Two Address Instructions
| 0 2 | 3 | 4 5 | 6 9 | 10 11 | 12 15 |
| Op Code | B | Td | D | Ts | S |
| Source Address when Ts = 2 |
| Destination Address when Td = 2 |
Format II – Jump Instructions and Bit I/O Instructions
| 0 7 | 8 15 |
| Op Code | Displacement |
Format III – Logical Instructions
| 0 5 | 6 9 | 10 11 | 12 15 |
| Op Code | D | Ts | S |
| Source Address when Ts = 2 |
Format IV – CRU Instructions
| 0 5 | 6 9 | 10 11 | 12 15 |
| Op Code | C | Ts | S |
| Source Address when Ts = 2 |
Format V – Register Shift Instructions
| 0 7 | 8 11 | 12 15 |
| Op Code | C | W |
Format VI – Single Address Instructions
| 0 9 | 10 11 | 12 15 |
| Op Code | Ts | S |
| Source Address when Ts = 2 |
Format VII – Control Instructions
Format VIIIa – Immediate Instructions
| 0 9 | 10 | 11 15 |
| Op Code | 0 | W |
| Data |
Format VIIIb – Implied Immediate Instructions
| 0 9 | 10 15 |
| Op Code | 000000 |
| Data |
Format VIIIc – Destination Workspace Register Instructions
Format IXa – Extended Operation Instruction
| 0 5 | 6 9 | 10 11 | 12 15 |
| Op Code | X | Ts | S |
| Source Address when Ts = 2 |
Format IXb – Multiply and Divide Instructions
This is the same as Format III but is used for a different type of instructions
| 0 5 | 6 9 | 10 11 | 12 15 |
| Op Code | D | Ts | S |
| Source Address when Ts = 2 |
Instructions
Operands
A subscript s indicates it's the source operand and a subscript d indicates it's destination operand
General Address (ga)
Specifies a workspace register or memory location, see Addressing Modes and Addressing Mode instruction field for description
Workspace Register Address (wa)
Specifies a workspace register
Immediate Operand (iop)
The word following this instruction
Displacement (disp)
A signed offset
Expression (exp)
An expression that results in an Address
Count (cnt) and Shift Count (scnt)
A count of bits
Extended Operation (xop)
The extended operation number used by the XOP instruction
Format Definitions
The format columns indicate the opcode if all modifier bits were 0
Data Transfer Instructions
Load Immediate (LI)
Stores in the immediate operand in the specified workspace register
| Instruction | Format | Binary Opcode | Octal | Hex |
| LI wa, iop | VIIIa | 0000001000000000 | 001000 | 0200 |
Load Interrupt Mask Immediate (LIMI)
Places the low order four bits of the immediate operand in the interrupt mask
| Instruction | Format | Binary Opcode | Octal | Hex |
| LIMI iop | VIIIb | 0000001100000000 | 001400 | 0300 |
Load Workspace Pointer Immediate (LWPI)
Stores the immediate operand in WP
| Instruction | Format | Binary Opcode | Octal | Hex |
| LWPI iop | VIIIb | 0000001011100000 | 001340 | 02E0 |
Move Words (MOV)
Replaces the destination word operand with the value of the source word operand
| Instruction | Format | Binary Opcode | Octal | Hex |
| MOV gas, gad | I | 1100000000000000 | 140000 | C000 |
Move Bytes (MOVB)
Replaces the destination byte operand with the value of the source byte operand. For workspace registers, only the high byte is used and updated.
| Instruction | Format | Binary Opcode | Octal | Hex |
| MOVB gas, gad | I | 1101000000000000 | 150000 | D000 |
Swap Bytes (SWPB)
Swaps the first and second byte of the operand
| Instruction | Format | Binary Opcode | Octal | Hex |
| SWPB gas | VI | 0000011011000000 | 003300 | 06C0 |
Store Status (STST)
Stores ST in the specified workspace register
| Instruction | Format | Binary Opcode | Octal | Hex |
| STST wa | VIIIc | 0000001011000000 | 001300 | 02C0 |
Store Workspace Pointer (STWP)
Store WP in the specified workspace register
| Instruction | Format | Binary Opcode | Octal | Hex |
| STWP wa | VIIIc | 0000001010100000 | 001240 | 02A0 |
Addition Instructions
Add Immediate (AI)
Adds the immediate word operand to the workspace register and stores the result in the workspace register
| Instruction | Format | Binary Opcode | Octal | Hex |
| AI wa, iop | VIIIa | 0000001000100000 | 001040 | 0220 |
Add Words (A)
Adds the two word operands together and stores them in the destination operand
| Instruction | Format | Binary Opcode | Octal | Hex |
| A gas,gad | I | 1010000000000000 | 120000 | A000 |
Add Bytes (AB)
Adds the two byte operands together and stores them in the destination operand. For workspace registers, only the high byte is used and updated.
| Instruction | Format | Binary Opcode | Octal | Hex |
| AB gas,gad | I | 1011000000000000 | 130000 | B000 |
Subtraction Instructions
Subtract Words (S)
Subtracts the source operand word from the destination operand word and stores the result in the destination operand
| Instruction | Format | Binary Opcode | Octal | Hex |
| S gas,gad | I | 0110000000000000 | 060000 | 6000 |
Subtract Bytes (SB)
Subtracts the source operand byte from the destination operand byte and stores the result in the destination operand. For workspace registers, only the high byte is used and updated.
| Instruction | Format | Binary Opcode | Octal | Hex |
| SB gas,gad | I | 0111000000000000 | 070000 | 7000 |
Multiplication and Division Instructions
Both the Multiply and the divide instructions use a consecutive 2-word area of the workspace, the multiply instruction uses it for one of the values to multiply and the divide instruction uses it to store the results.
In both cases the first portion is stored in the specified workspace register and the second portion is stored in the following register. If register 15 is specified then the second portion will be stored in the word after the workspace
Multiply (MPY)
Multiplies the destination workspace register by the source operand and store the result in the workspace register and word following it. The result is stored as a big-endian 32-bit value
| Instruction | Format | Binary Opcode | Octal | Hex |
| MPY gas,wad | IXb | 0011100000000000 | 034000 | 3800 |
Divide (DIV)
Divides the 32-bit big-endian value made up of the destination workspace register and the word following it by the source operand. The quotient is stored in the destination workspace register and the remainder is stored in the word following it.
| Instruction | Format | Binary Opcode | Octal | Hex |
| DIV gas,wad | IXb | 0011110000000000 | 036000 | 3C00 |
Increment and Decrement Instructions
Increment (INC)
Adds one to the source operand and stores the result in the source operand
| Instruction | Format | Binary Opcode | Octal | Hex |
| INC gas | VI | 0000010110000000 | 002600 | 0580 |
Increment by Two (INCT)
Adds two to the source operand and stores the result in the source operand
| Instruction | Format | Binary Opcode | Octal | Hex |
| INCT gas | VI | 0000010111000000 | 002700 | 05C0 |
Decrement (DEC)
Subtracts one from the source operand and stores the result in the source operand
| Instruction | Format | Binary Opcode | Octal | Hex |
| DEC gas | VI | 0000011000000000 | 003000 | 0600 |
Decrement by Two (DECT)
Subtracts two from the source operand and stores the result in the source operand
| Instruction | Format | Binary Opcode | Octal | Hex |
| DECT gas | VI | 0000011001000000 | 003100 | 0640 |
Sign Instructions
Absolute Value (ABS)
Computes the absolute value of the source operand and stores the result in the source operand. If the value is negative it will compute the 2's completement of the value, otherwise the value will be unchanged
| Instruction | Format | Binary Opcode | Octal | Hex |
| ABS gas | VI | 0000011101000000 | 003500 | 0740 |
Negate (NEG)
Compute's the 2's complement of the source operand and stores the result in the source operand
| Instruction | Format | Binary Opcode | Octal | Hex |
| NEG gas | VI | 0000010100000000 | 002400 | 0500 |
Shift Instructions
For shift instructions, if scnt is 0 then the contents are shifted by the value of the four least significant bits of workspace register 0. If the least significant bits are also 0, then the value is shifted 16 bits
Shift Right Arithmetic (SRA)
Shifts the contents of the workspace register to the right the specified number of bits, filling vacated bits with the sign bit.
| Instruction | Format | Binary Opcode | Octal | Hex |
| SRA wa, scnt | V | 0000100000000000 | 004000 | 0800 |
Shift Left Arithmetic (SLA)
Shifts the contents of the workspace register to the left the specified number of bits, filling vacated bits with 0
| Instruction | Format | Binary Opcode | Octal | Hex |
| SLA wa, scnt | V | 0000101000000000 | 005000 | 0A00 |
Shift Right Logical (SRL)
Shifts the contents of the workspace register to the right the specified number of bits, filling vacated bits with 0.
| Instruction | Format | Binary Opcode | Octal | Hex |
| SRL wa, scnt | V | 0000100100000000 | 004400 | 0900 |
Shift Right Circular (SRC)
Shifts the contents of the workspace register to the right the specified number of bits, filling vacated bits with the bits shifted out of the right
| Instruction | Format | Binary Opcode | Octal | Hex |
| SRC wa, scnt | V | 0000101100000000 | 005400 | 0B00 |
Logical Instructions
AND Immediate (ANDI)
ANDs the immediate operand with the specified workspace register and stores the result in the workspace register
| Instruction | Format | Binary Opcode | Octal | Hex |
| ANDI wa, iop | VIIIa | 0000001001000000 | 001100 | 0240 |
OR Immediate (ORI)
ORs the immediate operand with the specified workspace register and stores the result in the workspace register
| Instruction | Format | Binary Opcode | Octal | Hex |
| ORI wa,iop | VIIIa | 0000001001100000 | 001140 | 0260 |
Exclusive OR (XOR)
Exclusive ORs the source operand with the destination workspace register and stores the result in the workspace register
| Instruction | Format | Binary Opcode | Octal | Hex |
| XOR gas, wad | III | 0010100000000000 | 024000 | 2800 |
Invert (INV)
Inverts each bit of the operand and stores the result in the operand
| Instruction | Format | Binary Opcode | Octal | Hex |
| INV gas | VI | 0000010101000000 | 002500 | 0540 |
Clear (CLR)
Sets all of the bits in the source operand to 0 and stores the result in the operand
| Instruction | Format | Binary Opcode | Octal | Hex |
| CLR gas | VI | 0000010011000000 | 002300 | 04C0 |
Set to One (SETO)
Sets all of the bits in the source operand to 1 and stores the result in the operand
| Instruction | Format | Binary Opcode | Octal | Hex |
| SETO gas | VI | 0000011100000000 | 003400 | 0700 |
Set Ones Corresponding (SOC)
For each 1 bit in the source word operand, set the bit in the destination word operand to 1 and stores the result in the destination operand. All other bits are unaffected
| Instruction | Format | Binary Opcode | Octal | Hex |
| SOC gas, gad | I | 1110000000000000 | 160000 | E000 |
Set Ones Corresponding, Byte (SOCB)
For each 1 bit in the source byte operand, set the bit in the destination byte operand to 1 and stores the result in the destination operand. All other bits are unaffected. For workspace registers, only the high byte is used and updated.
| Instruction | Format | Binary Opcode | Octal | Hex |
| SOCB gas, gad | I | 1111000000000000 | 170000 | F000 |
Set Zeros Corresponding (SZC)
For each 1 bit in the source word operand, set the bit in the destination word operand to 0 and stores the result in the destination operand. All other bits are unaffected
| Instruction | Format | Binary Opcode | Octal | Hex |
| SZC gas, gad | I | 0100000000000000 | 040000 | 4000 |
Set Zeros Corresponding, Byte (SZCB)
For each 1 bit in the source byte operand, set the bit in the destination byte operand to 0 and stores the result in the destination operand. All other bits are unaffected. For workspace registers, only the high byte is used and updated.
| Instruction | Format | Binary Opcode | Octal | Hex |
| SZCB gas, gad | I | 0101000000000000 | 050000 | 5000 |
Compare Instructions
Compare Words (C)
Compares the source operand word to the destination operand word and updates the Logical Greater than, Arithmetic Greater Than and Equal status flags based on the comparison
| Instruction | Format | Binary Opcode | Octal | Hex |
| C gas,gad | I | 1000000000000000 | 100000 | 8000 |
Compare Bytes (CB)
Compares the source operand byte to the destination operand byte and updates the Logical Greater than, Arithmetic Greater Than and Equal status flags based on the comparison. If the source operand contains an odd number of 1 bits then the parity status flag will be set.
| Instruction | Format | Binary Opcode | Octal | Hex |
| CB gas,gad | I | 1001000000000000 | 110000 | 9000 |
Compare Immediate (CI)
Compares the source workspace register to the immediate operand word and updates the Logical Greater than, Arithmetic Greater Than and Equal status flags based on the comparison
| Instruction | Format | Binary Opcode | Octal | Hex |
| CI wa, iop | VIIIa | 0000001010000000 | 001200 | 0280 |
Compare Ones Corresponding (COC)
For each 1 bit in the source operand, checks if the corresponding bit in the destination workspace register is a 1. If all of the checked bits in the destination register are 1s then the Equal status flag is set to 1, otherwise the Equal status flag is set to 0
| Instruction | Format | Binary Opcode | Octal | Hex |
| COC gas,wad | III | 0010000000000000 | 020000 | 2000 |
Compare Zeros Corresponding (CZC)
For each 1 bit in the source operand, checks if the corresponding bit in the destination workspace register is a 0. If all of the checked bits in the destination register are 0s then the Equal status flag is set to 1, otherwise the Equal status flag is set to 0
| Instruction | Format | Binary Opcode | Octal | Hex |
| CZC gas,wad | III | 0010010000000000 | 022000 | 2400 |
CRU Instructions
CRU instructions use workspace register 12 as the base CRU address but only bits 3 through 14 are significant and get treated as a 12-bit number. Instructions that provide a displacement are shifted to the left one bit and added to workspace register 12 to give an affective CRU address.
Set Bit to Logical One (SBO)
Adds the displacement to the base CRU address and sets the CRU bit at the corresponding address to 1
| Instruction | Format | Binary Opcode | Octal | Hex |
| SBO disp | II | 0001110100000000 | 016400 | 1D00 |
Set Bit to Logical Zero (SBZ)
Adds the displacement to the base CRU address and sets the CRU bit at the corresponding address to 0
| Instruction | Format | Binary Opcode | Octal | Hex |
| SBZ disp | II | 0001111000000000 | 017000 | 1E00 |
Test Bit (TB)
Adds the displacement to the base CRU address and tests the value of the CRU bit at the corresponding address by updating the Equal status bit
| Instruction | Format | Binary Opcode | Octal | Hex |
| TB disp | II | 0001111100000000 | 017400 | 1F00 |
Load CRU (LDCR)
Transfers cnt number of bits from the source operand to the base CRU address
If the number of bits to transfer is less than or equal to 8 then the operand is a byte address, otherwise it is a word address. When cnt is 0 then 16 bits are transferred. Bits are transferred starting with the least significant bit and going towards the most significant bit. The CRU address used is incremented for each bit sent but workspace register 12 is not changed.
| Instruction | Format | Binary Opcode | Octal | Hex |
| LDCR gas, cnt | IV | 0011000000000000 | 030000 | 3000 |
Store CRU (STCR)
Transfers cnt number of bits to the source operand from the base CRU address
If the number of bits to transfer is less than or equal to 8 then the operand is a byte address, otherwise it is a word address. When cnt is 0 then 16 bits are transferred. Bits are stored starting with the least significant bit and going towards the most significant bit. The CRU address used is incremented for each bit sent but workspace register 12 is not changed.
Unused bits are reset to 0
| Instruction | Format | Binary Opcode | Octal | Hex |
| STCR gas, cnt | IV | 0011010000000000 | 032000 | 3400 |
Branch and Jump Instructions
Branch (B)
Replaces the PC with the source operand and starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| B gas | VI | 0000010001000000 | 002100 | 0440 |
Branch and Link (BL)
Replaces the PC with the source operand, stores the address of the instruction following this one in workspace register 11 and starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| BL gas | VI | 0000011010000000 | 003200 | 0680 |
Branch and Load Workspace Pointer (BLWP)
Replaces the WP with the source operand, the PC with the word following the source operand. Places the previous WP in the new workspace register 13, the previous PC (Now pointing at the next instruction) in the new workspace register 14 and the ST in the new workspace register 15. After storing all the value, starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| BLWP gas | VI | 0000010000000000 | 002000 | 0400 |
Unconditional Jump (JMP)
Adds the displacement to PC and starts executing at the new location. At the time of the addition, the PC will be pointing at the following instruction and the jump will be relative to that instruction
| Instruction | Format | Binary Opcode | Octal | Hex |
| JMP exp | II | 0001000000000000 | 010000 | 1000 |
Jump if Logical High (JH)
If the Logical Greater than is 1 and Equal is 0, adds the displacement to PC and starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| JH exp | II | 0001101100000000 | 015400 | 1B00 |
Jump if Logical Low (JL)
If the Logical Greater than is 0 and Equal is 0, adds the displacement to PC and starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| JL exp | II | 0001101000000000 | 015000 | 1A00 |
Jump if High or Equal (JHE)
If the Logical Greater than is 1 or Equal is 1, adds the displacement to PC and starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| JHE exp | II | 0001010000000000 | 012000 | 1400 |
Jump if Low or Equal (JLE)
If the Logical Greater than is 0 or Equal is 1, adds the displacement to PC and starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| JLE exp | II | 0001001000000000 | 011000 | 1200 |
Jump if Greater Than (JGT)
if Arithmetic Greater Than is 1, adds the displacement to PC and starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| JGT exp | II | 0001010100000000 | 012400 | 1500 |
Jump if Less Than (JLT)
if Arithmetic Greater Than is 0 and equal is 0, adds the displacement to PC and starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| JLT exp | II | 0001000100000000 | 010400 | 1100 |
Jump if Equal (JEQ)
if equal is 1, adds the displacement to PC and starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| JEQ exp | II | 0001001100000000 | 011400 | 1300 |
Jump if Not Equal (JNE)
if equal is 0, adds the displacement to PC and starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| JNE exp | II | 0001011000000000 | 013000 | 1600 |
Jump on Carry (JOC)
if carry is 1, adds the displacement to PC and starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| JOC exp | II | 0001100000000000 | 014000 | 1800 |
Jump if No Carry (JNC)
if carry is 0, adds the displacement to PC and starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| JNC exp | II | 0001011100000000 | 013400 | 1700 |
Jump if No Overflow (JNO)
if overflow is 0, adds the displacement to PC and starts executing at the new locationv
| Instruction | Format | Binary Opcode | Octal | Hex |
| JNO exp | II | 0001100100000000 | 014400 | 1900 |
Jump if Odd Parity (JOP)
if odd parity is 1, adds the displacement to PC and starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| JOP exp | II | 0001110000000000 | 016000 | 1C00 |
Extended Operation (XOP)
The xop value indicates which extended operation to perform. Between 0x0040 and 0x0079 are a series of transfer vectors. The first word indicates the WP to use during the XOP and the second word indicates the PC value for the start of the XOP code. The transfer vector is determined by multiplying the xop value by 4 and adding the result to 0x0040.
The effective address of the source operand is placed in workspace register 11 of the XOP workspace. The previous values of WP, PC and ST are stored in the new workspace register 13, 14 and 15 respectively. After storing all the value, starts executing with the WP and PC value specified by the transfer vector
| Instruction | Format | Binary Opcode | Octal | Hex |
| XOP gas, xop | IXa | 0010110000000000 | 026000 | 2C00 |
Return Instructions
Return with Workspace Pointer (RTWP)
Replaces WP with the contents of workspace register 13, the PC with workspace register 14 and ST with workspace register 15. After values are restored, resume execution at the previous location
| Instruction | Format | Binary Opcode | Octal | Hex |
| RTWP | VII | 0000001110000000 | 001600 | 0380 |
Execution Instructions
Execute (X)
Executes the source operand as an instruction. If the instruction would have subsequent words, then the words following the execute instruction are used.
| Instruction | Format | Binary Opcode | Octal | Hex |
| X gas | VI | 0000010010000000 | 002200 | 0480 |
Machine Instructions
Reset (RSET)
Clears the interrupt mask, resets directly connected I/O devices and any CRU devices that support it. Resets pending interrupts and turns the clock off
| Instruction | Format | Binary Opcode | Octal | Hex |
| RSET | VII | 0000001101100000 | 001540 | 0360 |
Idle (IDLE)
Places the CPU in the idle state
| Instruction | Format | Binary Opcode | Octal | Hex |
| IDLE | VII | 0000001101000000 | 001500 | 0340 |
Clock Off (CKOF)
Stop the line frequency clock and the clock interrupt
| Instruction | Format | Binary Opcode | Octal | Hex |
| CKOF | VII | 0000001111000000 | 001700 | 03C0 |
Clock On (CKON)
Enable the line frequency clock, starts the clock interrupt if enabled
| Instruction | Format | Binary Opcode | Octal | Hex |
| CKON | VII | 0000001110100000 | 001640 | 03A0 |
Load or Restart Execution (LREX)
Places the contents of location FFFC into WP and the contents of FFFE into PC. Stores the previous values of WP, PC and ST in the new workspace register 13, 14 and 15 respectively. Clears interrupt mask and starts executing at the new location
| Instruction | Format | Binary Opcode | Octal | Hex |
| LREX | VII | 0000001111100000 | 001740 | 03E0 |